AVG IDENTITY PROTECTION - V 90.2 Specifications download pdf (Page 22)

INA226

SBOS547 –JUNE 2011

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AFF: Alert Function Flag

Bit 4 While only one Alert Function can be monitored at the Alert pin at a time, the Conversion Ready can also be

enabled to assert the Alert pin. Reading the Alert Function Flag following an alert allows the user to determine if the

Alert Function was the source of the Alert.

When the Alert Latch Enable bit is set to Latch mode, the Alert Function Flag clears only when the Mask/Enable

following the next conversion that does not result in an Alert condition.

CVRF: Conversion Ready Flag

Bit 3 Although the INA226 can be read at any time, and the data from the last conversion is available, the Conversion

Ready bit is provided to help coordinate one-shot or triggered conversions. The Conversion bit is set after all

conversions, averaging, and multiplications are complete. Conversion Ready clears under the following conditions:

1.) Writing to the Configuration Register (except for Power-Down or Disable selections)

2.) Reading the Mask/Enable Register

OVF: Math Overflow Flag

Bit 2 This bit is set to '1' if an arithmetic operation resulted in an overflow error. It indicates that current and power data

may be invalid.

APOL: Alert Polarity bit; sets the Alert pin polarity.

Bit 1 1 = Inverted (active-high open collector)

0 = Normal (active-low open collector) (default)

LEN: Alert Latch Enable; configures the latching feature of the Alert pin and Flag bits.

Bit 0 1 = Latch enabled

0 = Transparent (default)

When the Alert Latch Enable bit is set to Transparent mode, the Alert pin and Flag bits will reset to their idle states

when the fault has been cleared. When the Alert Latch Enable bit is set to Latch mode, the Alert pin and Flag bits

will remain active following a fault until the Mask/Enable Register has been read.

Alert Limit 07h (Read/Write)

The Alert Limit Register contains the value used to compare to the register selected in the Mask/Enable Register

to determine if a limit has been exceeded.

BIT # D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

BIT

AUL15 AUL14 AUL13 AUL12 AUL11 AUL10 AUL9 AUL8 AUL7 AUL6 AUL5 AUL4 AUL3 AUL2 AUL1 AUL0

NAME

POR

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

VALUE

BUS OVERVIEW

The INA226 offers compatibility with both I

C and SMBus interfaces. The I

C and SMBus protocols are

essentially compatible with one another.

The I

C interface is used throughout this data sheet as the primary example, with SMBus protocol specified only

when a difference between the two systems is discussed. Two bidirectional lines, SCL and SDA, connect the

INA226 to the bus. Both SCL and SDA are open-drain connections.

The device that initiates a data transfer is called a master, and the devices controlled by the master are slaves.

The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access,

and generates START and STOP conditions.

To address a specific device, the master initiates a start condition by pulling the data signal line (SDA) from a

high to a low logic level while SCL is high. All slaves on the bus shift in the slave address byte on the rising edge

of SCL, with the last bit indicating whether a read or write operation is intended. During the ninth clock pulse, the

slave being addressed responds to the master by generating an Acknowledge and pulling SDA low.

Product Folder Link(s): INA226

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AVG IDENTITY PROTECTION - V 90.2 Specifications Page 22

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